In some data transmission systems, data is transmitted from a first integrated circuit to a second integrated circuit through one or more external conductors. A transmitter circuit in the first integrated circuit transmits the data to a receiver circuit in the second integrated circuit in response to a transmitter clock signal. The receiver circuit samples the data in response to a receiver clock signal.
A clock signal in the second integrated circuit is used to generate the receiver clock signal. The clock signal may be transmitted from the second integrated circuit to the first integrated circuit to generate the transmitter clock signal. The transmitter clock signal is provided to the transmitter circuit in the first integrated circuit through a clock distribution network. Temperature and voltage variations in the first integrated circuit may cause the clock distribution network to generate drift in the transmitter clock signal. The drift in the transmitter clock signal causes the transmitter circuit to introduce timing offsets into the data signals. Timing offsets in the data signals received from the transmitter circuit relative to the receiver clock signal may cause the receiver circuit to sample the data signals at the wrong time, generating incorrect data values.
A phase-locked loop or a delay-locked loop can be used in the first integrated circuit to reduce the effect of drift in the transmitter clock signal. However, phase-locked loops (PLLs) and delay-locked loops (DLLs) require additional die area and may consume a significant amount of power. Also, PLLs and DLLs are slow to lock the phase and frequency of an output clock signal to the phase and frequency of a reference clock signal after waking up from a low power state.